Systems for storing large amounts of data implement various kinds of mechanisms meant to enhance the level of performance and reliability. Among bottlenecks typically having a negative impact on the ability of a storage system to perform with high levels of throughput and with low latency, is performance of the system's disk drives. Rapid access to data stored on disk media is an important concern in the design of high performance computer systems. Problems of enhancing performance of the disc drives have been recognized in the Prior Art and various systems have been developed to provide a solution as, for example:
U.S. Pat. No. 6,029,226 (Ellis et al.) discloses a method and apparatus for writing data to a storage device such as a hard disk drive in which two write commands from an initiator are processed as a single command at the storage device. A first request is received from a small computer systems interface (SCSI) bus to write a first set of data to a storage device. The first set of data is transferred to memory for temporary storage prior to transfer to the storage device. Thereafter, a second write request is received to write a second set of data to the storage device in which the write request includes a logical block address. An ending logical block address determined after transferring the first set of data is compared to the logical block address of the second request to determine whether the second set of data can be written to the storage device along with the first set of data as a single write operation based on the comparison of the logical block address of the second request and the ending logical block address. In response to a determination that the first set of data and the second set of data can be written to the disk as a single write operation, the second set of data is written to the memory as a part of the first write request.
U.S. Pat. No. 6,209,058 (Shats et al.) discloses a method of data transfer in a cache system comprising a cache buffer including a plurality of data blocks for storing data, and a cache manager for retrieving data from a disk drive and storing the data into the cache buffer. The disk drive includes a data disk having a plurality of concentric data tracks thereon, a spindle motor for rotating the data disk, and a transducer supported by a carrier for positioning the transducer over individual data tracks to write data thereto or read data therefrom. In one embodiment, a method of data transfer in response to a request for retrieving a set of data blocks from the selected track, comprises the steps of: (a) defining a data segment on the selected track, wherein the data segment comprises, in sequence, a pre-fetch data area, a fetch data area comprising the set of data blocks, and a post-fetch data area; (b) determining a landing position of the transducer over the selected track relative to the data segment; and (c) controlling transfer of data from the data segment to the cache buffer based on the landing position relative to the data segment, thus maximizing the data read from the data segment without increasing rotational latency.
U.S. Pat. No. 6,693,766 (Wilkes et al.) discloses an apparatus for surface-based data mapping for a disk drive system and a method of operation in which adjacent data tracks on the data storage surfaces of a disk drive are grouped into data track sets and data track sets on different data storage surfaces are grouped into bunches. The bunches are used to determine how to perform the logical to physical data layout mapping inside the disk drive. A disk drive controller controls disk read/write heads and provides a data layout mapping that maps logically adjacent data blocks to a data track, then to an adjacent data track radially along the same surface in a data track set in a bunch, and then to a different data track in a different data track set in the bunch.
U.S. Pat. No. 6,684,287 (Spencer) discloses a method of writing to a hard disk drive using effective track skew different from the track skew used when reading from the disk. During reads from the disk, the disk controller uses a traditional logical track layout and logical block address (LBA) numbering having a track skew value related to read settle time. A different effective track skew value, optimized for write settle time, is used, however, when writing to the disk. Logical blocks are written to the disk out-of-sequence in order to accommodate this different effective track skew value.
U.S. Pat. No. 7,047,357 discloses a striping disk controller and disk drive system for a computer system. The striping disk controller and disk drive system include an interface connected to the system bus and communicating with the BIOS; first and second disk drives each having data separator electronics, data formatting electronics and head positioning electronics, and a striping controller connected between the first and second disk drives and the interface, the striping controller adapted to cause data being communicated between the system bus and the first and second drives to be written to and read from the first and second drives in an interleaved form and substantially in parallel.
US Patent Application No. 2003/202270 (Ng et al.) discloses a disc drive with a disc having multiple concentric data tracks. A track start point is rotationally displaced by a track skew time relative to a track start point of an adjacent concentric data tracks. The read/write head has a write settling time that is more than the track skew time. A data reordering circuit and firmware reorders write data and provides the reordered data to the read/write head after the write settling time. The reordering of the write data reduces write latency.
US Patent Application 2005/015543 (Krantz et al.) discloses a hard disk unit including a disk, a controller microprocessor, a host bus interface, a buffer memory, a buffer memory controller, and a disk formatter. The bus interface receives write operations, and corresponding write operation data is stored in the buffer memory. The buffer memory controller includes address registers and block count registers. The microprocessor loads the address registers with the buffer memory addresses of multiple write operations and loads the block count registers with the size of the corresponding data. The microprocessor then issues a single command to the buffer memory controller to transfer the data from the buffer memory to the disk formatter. The address registers and block count registers enable the data of multiple write operations to be transferred and written to a disk in an order other than the order in which the write operations were received at the bus interface.